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AT45DB321C
6.3.1
Erasing the Sector Protection Register
To erase the Sector Protection Register, the CS pin must first be asserted. Once the CS pin has
been asserted, the 4-byte erase command sequence must be clocked in via the SI (serial input)
pin. After the last bit of the command sequence has been clocked in, the CS pin must be deas-
serted to initiate the internally self-timed erase cycle (t PE ). The Ready/Busy status will indicate
that the device is busy during the erase cycle. The erased state of each bit (of a byte) in the Sec-
tor Protection Register indicates that the corresponding sector is flagged for protection. The
RESET pin is disabled during this erase cycle to prevent incomplete erasure of the Sector Pro-
tection Register.
Command
Erase Sector Protection Register
Byte 1
3DH
Byte 2
2AH
Byte 3
7FH
Byte 4
CFH
6.3.2
Programming the Sector Protection Register
To program the Sector Protection Register, the CS pin must first be asserted. Once the CS pin
has been asserted, the 4-byte command sequence must be clocked in via the SI (serial input)
pin. After the last bit of the command sequence has been clocked in, the data for the contents of
the Sector Protection Register must be clocked in. The first byte corresponds to sector 0 (0a,
0b), the second byte corresponds to Sector 1 and the last byte (byte 16) corresponds to Sector
15. After the last bit of data has been clocked in, the CS pin must be deasserted to initiate the
internally self-timed program cycle (t P ). The Ready/Busy status will indicate that the device is
busy during the program cycle. The RESET pin is disabled during this program cycle to prevent
incomplete programming of the sector protection register.
Command
Program Sector Protection Register
Byte 1
3DH
Byte 2
2AH
Byte 3
7FH
Byte 4
FCH
6.3.3
Reading the Sector Protection Register
To read the Sector Protection Register, the CS pin must first be asserted. Once the CS pin has
been asserted, a 4-byte command sequence 32H, 00H, 00H, 00H and 32 don’t care clock cycles
must be clocked in via the SI (serial input) pin. The 32 don’t care clock cycles are required to ini-
tialize the read operation. After the 32 don’t care clock cycles, any additional clock pulses on the
SCK pin will result in data being output on the SO (serial output) pin. The read will begin with
Byte_1 of the Sector Protection Register for Sector_0, followed with Byte_2 for Sector_1. The
read operation will continue until Byte_16 for Sector_15 is read. Once the last byte is read a low-
to-high transition on the CS pin is required to terminate the read operation.
Command
Read Sector Protection Register
Byte 1
32H
Byte 2
00H
Byte 3
00H
Byte 4
00H
Note:
Next generation devices of the “D” family will not require the 32 don’t care clock cycles.
11
3387M–DFLASH–2/08
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